Integrated circuit memory circuits have been produced using MOS and bipolar technologies. The most complex memory circuits have been implemented using the MOS technology. The applications for MOS memory circuits, either random access memories (RAMs) or read only memories (ROMs) have required low cost and high speeds that strain capability of the MOS technology. To achieve the low cost, high density of memory elements on a chip is required. In order that such memory circuits be competitive, it has been necessary to minimize the amount of low density peripheral circuitry on the chip for address decoding, input/output circuitry and clock and timing signal generating circuitry. Therefore, circuits which have been commercially successful have required a plurality of externally generated clock signals and relatively simple decode input and output circuits. As a result, commercially successful MOS memory circuits produced to date have had peripheral circuitry which performed relatively simple decoding and input/output functions to allow interfacing with the memory array and have required close operating limits with respect to the timing of external clock signals, address signals and input/output signals. Relatively close tolerances of power supply voltages have been required to allow the circuit to operate within the timing specification ranges.
Micro-processor chips capable of receiving and executing multi-bit instructions and communicating with and addressing, writing in to and receiving data from external memory circuits have been implemented in MOS technologies. A considerable amount of "random logic" has been required to accomplish instruction decoding and execution of such micro-processor chips. This has been accomplished with individual combinational gates, shift registers and latches, all of which have a relatively low packing density in current MOS technology, but are the fastest means of accomplishing such functions. However, the low density and consequently large chip size required by this approach increases the cost and chip size of prior art micro-processor chips.